Vasilios Kelefouras

Academic profile

Dr Vasilios Kelefouras

Lecturer in Computer Science
School of Engineering, Computing and Mathematics (Faculty of Science and Engineering)

The Global Goals

In 2015, UN member states agreed to 17 global to end poverty, protect the planet and ensure prosperity for all. Vasilios's work contributes towards the following SDG(s):

Goal 04: SDG 4 - Quality EducationGoal 14: SDG 14 - Life Below Water

About Vasilios

I am a Lecturer (assistant professor) in Computer Science at the 麻豆传媒. My research develops methods that make AI run faster and with lower energy and memory use across diverse platforms, from edge devices to supercomputers. I work on compiler and runtime optimisation for HPC and high-performance embedded systems (CPUs/GPUs/NPUs/FPGAs), efficient DNN inference (compression via low-rank factorisation and pruning, memory-aware execution, adaptive networks), and performance optimisation of tensor/matrix computations for HPC and edge AI.

I welcome PhD applicants and industry collaborations in AI compilers, performance engineering, DNN compression, and efficient DNN training and inference on heterogeneous systems.

Research Interests:

  • AI compilers & performance engineering - hardware-aware optimisation across CPUs, GPUs, NPUs and FPGAs

  • Efficient DNN inference (model compression; memory & energy optimisation)

  • Adaptive networks (dynamic/conditional computation; compute鈥揳ccuracy trade-offs)

  • Tensor/matrix computation optimisation

  • Runtime/task scheduling and memory management for HPC/edge systems

Research Highlights:

  • ACM TECS 2025: Optimising Tensor Train decomposition for DNNs on RISC-V using design-space exploration and compiler optimisations, targeting efficient edge deployment.

  • ACM TECS 2025: Register blocking via a source-to-source, analytical modelling methodology for affine loop kernels, enabling predictable performance/portable optimisation.

  • DATE 2024: A CNN compression methodology for layer-wise rank selection that explicitly accounts for inter-layer interactions, improving compression decisions beyond per-layer heuristics.

  • IEEE TPDS 2023: Analytical CPU convolution methodology achieving 1.1脳鈥7.2脳 speedups vs oneDNN on ResNet-50/DenseNet-121/SqueezeNet layers (112 layers; two platforms).

  • IEEE TPDS 2022: CPU 2D convolution methodology achieving 2.8脳鈥40脳 speedups vs Intel IPP/OpenCV on key image-processing kernels across multiple image sizes and platforms.

Awards:

  • HiPEAC Technology Transfer Award (2022) - technology transferred to Think Silicon.

  • Best Paper Award, SAMOS XXII - 鈥淎 Design Space Exploration Methodology for Enabling Tensor Train Decomposition in Edge Devices鈥.

Supervised Research Degrees

PhD Completions:
  1. 聽鈥淚mproving the performance of HiRep Lattice Simulations software by exploiting the CPU/GPU hardware architecture details and algorithm characteristics鈥, Main Supervisor (DoS) for Dr. Shidur Rahman (2020-2024)
  2. 聽"Optimising Flow Routing Using Network Performance Analysis", 2nd Supervisor for Dr Muna Al-Saadi (2020-2023)聽

Teaching

Currently, I am the module leader of the following modules
  • Parallel Computing (COMP3001)
  • Computer Systems (COMP1001)
  • Computing Practice (COMP1004)
Admin Roles
  • Applicant Day Lead for six CS Programs (2023-present)聽
  • Admissions Tutor for six CS Programs (2023-present)
  • Academic Liaison Person for seven Computing Partner Colleges (2019-present)
  • Coordinator of International Partnerships agreements for computing (2023-present)
  • HPC Champion (Computing) and HPC Steering Committee member, (2022鈥損resent).
  • EDI Committee Member (2022-23)

Contact Vasilios

B330, Portland Square, Drake Circus, 麻豆传媒, PL4 8AA
+44 1752 586339